A field-programmable gate array is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. A semiconductor' is a Solid material that has Electrical conductivity in between a conductor and an insulator; it can vary over that A programmable logic device or PLD is an electronic component used to build reconfigurable Digital circuits Unlike a Logic gate, which has a Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. A logic gate performs a logical operation on one or more logic inputs and produces a single logic output Symbols There are two symbols for XOR gates the 'military' symbol and the 'rectangular' symbol In Digital circuit theory combinational logic (also called combinatorial logic) is a type of logic circuit whose output is a Pure function of the In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. In Digital circuits a flip-flop is a term referring to an Electronic circuit (a Bistable Multivibrator) that has two stable states and thereby
A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. A breadboard ( solderless breadboard, protoboard, plugboard) is a reusable Solderless device used to build a (generally temporary Prototype Logic blocks and interconnects can be programmed by the customer or designer, after the FPGA is manufactured, to implement any logical function—hence the name "field-programmable". An electronic device or Embedded system is said to be field-programmable or in-place programmable if its Firmware (stored in Non-volatile
FPGAs are usually slower than their application-specific integrated circuit (ASIC) counterparts, cannot handle as complex a design, and draw more power (for any given semiconductor process). In the Microelectronics industry a semiconductor fabrication plant (commonly called a fab) is a factory where devices such as Integrated circuits are manufactured But their advantages include a shorter time to market, ability to re-program in the field to fix bugs, and lower non-recurring engineering costs. In Commerce, time to market ( TTM) is the length of time it takes from a product being conceived until its being available for sale Non-recurring engineering ( NRE) refers to the one-time cost of researching designing and testing a new product Vendors can sell cheaper, less flexible versions of their FPGAs which cannot be modified after the design is committed. The designs are developed on regular FPGAs and then migrated into a fixed version that more resembles an ASIC.
"Complex Programmable Logic Device" (CPLDs) are an alternative for simpler designs. A complex programmable logic device (CPLD is a Programmable logic device with complexity between that of PALs and FPGAs and architectural features of both They also retain their programming over powerdowns.
To configure ("program") an FPGA or CPLD you specify how you want the chip to work with a logic circuit diagram or a source code using a hardware description language (HDL). A circuit diagram (also known as an electrical diagram Wiring diagram, elementary diagram or electronic Schematic) is a simplified conventional pictorial representation In Computer science, source code (commonly just source or code) is any sequence of statements or declarations written in some Human-readable In Electronics, a hardware description language or HDL is any language from a class of Computer languages and/or Programming languages for formal The HDL form might be easier to work with when handling large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. On the other hand, schematic entry might allow for a more tight specification of what you want.
Going from schematic/HDL source files to actual configuration: The source files are fed to a software suite from the FPGA/CPLD vendor that through different steps will produce a file. This file is then transferred to the FPGA/CPLD via a serial interface (JTAG) interface or to external memory device like an EEPROM. In Telecommunication and Computer science, serial communication is the process of sending data one Bit at one time sequentially over a Communication Joint Test Action Group ( JTAG) is the usual name used for the IEEE 1149 EEPROM (also written E2PROM and pronounced e-e-prom or simply e-squared which stands for E lectrically E rasable P rogrammable
The historical roots of FPGAs are in complex programmable logic devices (CPLDs) of the early to mid 1980s. A complex programmable logic device (CPLD is a Programmable logic device with complexity between that of PALs and FPGAs and architectural features of both A Xilinx co-founder, Ross Freeman, invented the field programmable gate array in 1984. Ross Freeman was the inventor of the Field Programmable Gate Array ( FPGA) and along with Bernie Vonderschmitt, co-founded Xilinx, the leading FPGA developer CPLDs and FPGAs include a relatively large number of programmable logic elements. CPLD logic gate densities range from the equivalent of several thousand to tens of thousands of logic gates, while FPGAs typically range from tens of thousands to several million.
The primary differences between CPLDs and FPGAs are architectural. A CPLD has a somewhat restrictive structure consisting of one or more programmable sum-of-products logic arrays feeding a relatively small number of clocked registers. In Computer architecture, a processor register is a small amount of storage available on the CPU whose contents can be accessed more quickly than storage The result of this is less flexibility, with the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. The FPGA architectures, on the other hand, are dominated by interconnect. This makes them far more flexible (in terms of the range of designs that are practical for implementation within them) but also far more complex to design for.
Another notable difference between CPLDs and FPGAs is the presence in most FPGAs of higher-level embedded functions (such as adders and multipliers) and embedded memories.
Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running. Partial re-configuration is the process of configuring a portion of a Field programmable gate array while the other part is still running/operating
A recent trend has been to take the coarse-grained architectural approach a step further by combining the logic blocks and interconnects of traditional FPGAs with embedded microprocessors and related peripherals to form a complete "system on a programmable chip". This work mirrors the architecture by Ron Perlof and Hana Potash of Burroughs Advanced Systems Group which combined an reconfigurable CPU architecture on a single chip called the SB24. That work was done in 1982. Examples of such hybrid technologies can be found in the Xilinx Virtex-II PRO and Virtex-4 devices, which include one or more PowerPC processors embedded within the FPGA's logic fabric. PowerPC is a RISC Instruction set architecture created by the 1991 Apple – IBM – Motorola alliance known as AIM The Atmel FPSLIC is another such device, which uses an AVR processor in combination with Atmel's programmable logic architecture. The AVR is a Modified Harvard architecture 8-bit RISC single chip Microcontroller (µC which was developed by Atmel in 1996
An alternate approach to using hard-macro processors is to make use of "soft" processor cores that are implemented within the FPGA logic. In Electronic design a Semiconductor intellectual property core, IP block, IP core, or logic core is a reusable unit of logic cell (See "Soft processors" below).
As previously mentioned, many modern FPGAs have the ability to be reprogrammed at "run time," and this is leading to the idea of reconfigurable computing or reconfigurable systems — CPUs that reconfigure themselves to suit the task at hand. Reconfigurable computing is a computing paradigm combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing The Mitrion Virtual Processor from Mitrionics is an example of a reconfigurable soft processor that is implemented on FPGAs. Mitrionics is a Swedish company manufacturing softcore reconfigurable processors It does not however support dynamic reconfiguration at runtime, but instead adapts itself to a specific program.
Additionally, new, non-FPGA architectures are beginning to emerge. Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip. A microprocessor incorporates most or all of the functions of a Central processing unit (CPU on a single Integrated
There are many soft microprocessor cores available, both closed and open source. A soft microprocessor (also called softcore microprocessor or a soft processor) is a Microprocessor core that can be wholly implemented using Logic synthesis A soft microprocessor (also called softcore microprocessor or a soft processor) is a Microprocessor core that can be wholly implemented using Logic synthesis For a given CPU architecture, a hard (embedded) CPU core will outperform a soft-core CPU (i. e. , a programmable-logic implementation of the CPU). The following list is by no means exhaustive.
|Processor||Developer||Source code||Bus support||Notes||Project home|
|Nios, Nios II||Altera||Avalon, Wishbone||32-bit RISC architecture||Altera Nios II|
|TSK3000||Altium||WishBone||32-bit RISC Modified Harvard architecture||Altium TSK3000|
|TSK51x/52x||Altium||WishBone/80C51||8-bit 80C51 compatible, outperforms most 80C51 derivatives||TSK51x TSK52x|
|TSK80||Altium||Z80 bus||8-bit optimized Z80 instruction set compatible||TSK80|
|PacoBlaze||Pablo Bleyer||Compatible with the PicoBlaze processors||PacoBlaze|
|AEMB||Shawn Tan||Wishbone||MicroBlaze EDK 3. Nios II is a 32-bit embedded-processor architecture designed specifically for the Altera family of FPGA. Altera Corporation ( is one of the two major manufacturer of high-end PLDs ( Programmable logic devices, along with Xilinx. Altium or Altium Limited is Australian CAD/CAE software company listed on the Australian Stock Exchange (ASX code ALU The Wishbone Bus is an Open source hardware Computer bus intended to let the parts of an Integrated circuit communicate with each other Altium or Altium Limited is Australian CAD/CAE software company listed on the Australian Stock Exchange (ASX code ALU Altium or Altium Limited is Australian CAD/CAE software company listed on the Australian Stock Exchange (ASX code ALU Lattice Semiconductor Corporation ( is a United States based manufacturer of high-performance Programmable logic devices ( FPGAs, CPLDs & SPLDs PacoBlaze is a synthesizable and behavioral Verilog implementation of Xilinx 's PicoBlaze soft microcontroller core and is available through the BSD The Wishbone Bus is an Open source hardware Computer bus intended to let the parts of an Integrated circuit communicate with each other 2 compatible Verilog core||AEMB|
|Diamond 106Micro||Tensilica||PIF, AHB Lite, AXI||32-bit RISC architecture||Tensilica Diamond 106Micro|
|OpenFire||Virginia Tech CCM Lab||OPB, FSL||Binary compatible with the MicroBlaze||VT OpenFire|
|MicroBlaze||Xilinx||OPB, FSL, LMB, PLB||Xilinx MicroBlaze|
Applications of FPGAs include digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation and a growing range of other areas. Tensilcia is an IP core company based in Silicon Valley. Tensilica is best known for its Xtensa tool-generated Microprocessor cores that are particularly The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze processor The MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx. Xilinx Inc ( is the world's largest developer and fabless manufacturer of a class of reconfigurable hardware chips known as Field-programmable gate arrays PicoBlaze is the designation of a series of three free soft processor cores from Xilinx for use in their FPGA and CPLD products Xilinx Inc ( is the world's largest developer and fabless manufacturer of a class of reconfigurable hardware chips known as Field-programmable gate arrays Actel Corporation ( is a manufacturer of single-chip FPGA solutions Digital signal processing ( DSP) is concerned with the representation of the signals by a sequence of numbers or symbols and the processing of these signals A Software-Defined Radio (SDR system is a Radio communication system where components that have typically been implemented in hardware (i This article is about the field of research and industry for the corporation see The Aerospace Corporation Aerospace comprises the Defence Medical imaging refers to the techniques and processes used to create Images of the human body (or parts thereof for clinical purposes ( Medical procedures seeking to Computer vision is the science and technology of machines that see Speech recognition (also known as automatic speech recognition or computer speech recognition) converts spoken words to machine-readable input (for example to keypresses Cryptography (or cryptology; from Greek grc κρυπτός kryptos, "hidden secret" and grc γράφω gráphō, "I write" Bioinformatics is the application of information technology to the field of molecular biology An emulator duplicates (provides an emulation of the functions of one System using a different system so that the second system behaves like (and appears to FPGAs originally began as competitors to CPLDs and competed in a similar space, that of glue logic for PCBs. A complex programmable logic device (CPLD is a Programmable logic device with complexity between that of PALs and FPGAs and architectural features of both In Electronics, glue logic is the custom Electronic circuitry needed to achieve compatible interfaces between two (or more different off-the-shelf Integrated A printed circuit board, or PCB, is used to mechanically support and electrically connect Electronic components using conductive pathways or traces As their size, capabilities, and speed increased, they began to take over larger and larger functions to the state where some are now marketed as full systems on chips (SOC). System-on-a-chip or system on chip ( SoC or SOC) refers to integrating all components of a Computer or other electronic System
FPGAs especially find applications in any area or algorithm that can make use of the massive parallelism offered by their architecture. One such area is code breaking, in particular brute-force attack, of cryptographic algorithms. In Cryptanalysis, a brute force attack is a method of defeating a Cryptographic scheme by trying a large number of possibilities for example possible keys
FPGAs are increasingly used in conventional High Performance Computing applications where computational kernels such as FFT or Convolution are performed on the FPGA instead of a microprocessor. High-performance computing (HPC uses Supercomputers and Computer clusters to solve advanced computing problems In Mathematics and in particular Functional analysis, convolution is a mathematical operation on two functions f and A microprocessor incorporates most or all of the functions of a Central processing unit (CPU on a single Integrated The use of FPGAs for computing tasks is known as reconfigurable computing. Reconfigurable computing is a computing paradigm combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing
The inherent parallelism of the logic resources on the FPGA allows for considerable compute throughput even at a sub-500 MHz clock rate. For example, the current (2007) generation of FPGAs can implement around 100 single precision floating point units, all of which can compute a result every single clock cycle. In Computing, floating point describes a system for numerical representation in which a string of digits (or Bits represents a Real number. The flexibility of the FPGA allows for even higher performance by trading off precision and range in the number format for an increased number of parallel arithmetic units. This has driven a new type of processing called reconfigurable computing, where time intensive tasks are offloaded from software to FPGAs. Reconfigurable computing is a computing paradigm combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing
The adoption of FPGAs in high performance computing is currently limited by the complexity of FPGA design compared to conventional software and the extremely long turn-around times of current design tools, where 4-8 hours wait is necessary after even minor changes to the source code. In Computer science, source code (commonly just source or code) is any sequence of statements or declarations written in some Human-readable
The typical basic architecture consists of an array of configurable logic blocks (CLBs) and routing channels. Multiple I/O pads may fit into the height of one row or the width of one column in the array. Generally, all the routing channels have the same width (number of wires).
An application circuit must be mapped into an FPGA with adequate resources.
A classic FPGA logic block consists of a 4-input lookup table (LUT), and a flip-flop, as shown below. In Computer science, a lookup table is a Data structure, usually an Array or Associative array, often used to replace a runtime computation with In Digital circuits a flip-flop is a term referring to an Electronic circuit (a Bistable Multivibrator) that has two stable states and thereby In recent years, manufacturers have started moving to 6-input LUTs in their high performance parts, claiming increased performance. 
There is only one output, which can be either the registered or the unregistered LUT output. The logic block has four inputs for the LUT and a clock input. Since clock signals (and often other high-fanout signals) are normally routed via special-purpose dedicated routing networks in commercial FPGAs, they and other signals are separately managed.
For this example architecture, the locations of the FPGA logic block pins are shown below.
Each input is accessible from one side of the logic block, while the output pin can connect to routing wires in both the channel to the right and the channel below the logic block.
Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it.
Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the W wires (where W is the channel width) in the horizontal channel immediately below it.
Generally, the FPGA routing is unsegmented. That is, each wiring segment spans only one logic block before it terminates in a switch box. By turning on some of the programmable switches within a switch box, longer paths can be constructed. For higher speed interconnect, some FPGA architectures use longer routing lines that span multiple logic blocks.
Whenever a vertical and a horizontal channel intersect, there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure below illustrates the connections in a switch box.
Modern FPGA families expand upon the above capabilities to include higher level functionality fixed into the silicon. Having these common functions embedded into the silicon reduces the area required and gives those functions increased speed compared to building them from primitives. Examples of these include multipliers, generic DSP blocks, embedded processors, high speed IO logic and embedded memories.
FPGAs are also widely used for systems validation including pre-silicon validation, post-silicon validation, and firmware development. This allows chip companies to validate their design before the chip is produced in the factory, reducing the time to market.
To define the behavior of the FPGA the user provides a hardware description language (HDL) or a schematic design. In Electronics, a hardware description language or HDL is any language from a class of Computer languages and/or Programming languages for formal A schematic is a diagram that represents the elements of a System using abstract graphic Symbols rather than realistic pictures Common HDLs are VHDL and Verilog. In the Semiconductor and electronic design industry Verilog is a Hardware description language (HDL used to model electronic systems. Then, using an electronic design automation tool, a technology-mapped netlist is generated. Electronic design automation ( EDA) is the category of tools for designing and producing electronic systems ranging from The word netlist can be used in several different contexts but perhaps the most popular is in the field of Electronic design. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software. Place and Route is a stage in the design of Printed Circuit Boards Integrated Circuits, and Field programmable gate arrays As implied by the name it is The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation Simulation is the imitation of some real thing state of affairs or process Once the design and validation process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA.
In an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level of the design. See the terminology section below for information regarding inconsistent use of the terms assembly and assembler Companies such as Cadence, Synopsys and Celoxica are promoting SystemC as a way to combine high level languages with concurrency models to allow faster design cycles for FPGAs than is possible using traditional HDLs. Cadence Design Systems Inc ( is an Electronic design automation (EDA Software and engineering services company founded in 1988 by the merger of SDA Systems and Not to be confused with Synopsis Synopsys Inc is one of the largest companies in the Electronic design automation industry SystemC is often thought of as a hardware description language like VHDL and Verilog, but is more aptly described as a system description language Approaches based on standard C or C++ (with libraries or other extensions allowing parallel programming) are found in the Catapult C tools from Mentor Graphics, and in the Impulse C tools from Impulse Accelerated Technologies. tags please moot on the talk page first! --> In Computing, C is a general-purpose cross-platform block structured C++ (" C Plus Plus " ˌsiːˌplʌsˈplʌs is a general-purpose Programming language. Mentor Graphics Inc ( is a US -based multinational Corporation dealing in Electronic design automation (EDA for Electrical engineering and Impulse C is a subset of the C programming language combined with a C-compatible Function library supporting Parallel programming, in particular for Annapolis Micro Systems, Inc. 's CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry. National Instruments, or NI ( is an American company with over 4000 employees and direct operations in 41 countries Dataflow is a term used in Computing, and may have various shades of meaning Languages such as SystemVerilog, SystemVHDL, and Handel-C (from Celoxica) seek to accomplish the same goal, but are aimed at making existing hardware engineers more productive versus making FPGAs more accessible to existing software engineers. In the Semiconductor and electronic design industry SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based Handel-C is a programming language and Hardware Description Language (HDL for compiling programs into hardware images of FPGAs or ASICs It is There is more information on C to HDL and Flow to HDL in their respective articles. A number of vendors have attempted to create tools that convert C or C-like languages into a Hardware description language like VHDL or Verilog. This page is to describe tools and methods that convert Flow based system design into hardware description languages like VHDL or Verilog.
To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP suppliers (rarely free, and typically released under proprietary licenses). In Electronic design a Semiconductor intellectual property core, IP block, IP core, or logic core is a reusable unit of logic cell Other predefined circuits are available from developer communities such as OpenCores (typically free, and released under the GPL, BSD or similar license), and other sources. OpenCores is a loose community of people who are interested in developing Digital Open source hardware through Electronic design automation, with a similar Free software or software libre is Software that can be used studied and modified without restriction and which can be copied and redistributed in modified or unmodified BSD licenses represent a family of Permissive free software licences.
In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. In Integrated circuit design, Register Transfer Level ( RTL) description is a way of describing the operation of a synchronous Digital circuit In the Semiconductor and electronic design industry Verilog is a Hardware description language (HDL used to model electronic systems. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist.
As of late 2005, the FPGA market has mostly settled into a state where there are two major "general-purpose" FPGA manufacturers and a number of other players who differentiate themselves by offering unique capabilities.